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9 Module Description
9.1 Receiver (RX)
9.1.1 Overview
The Atmel AT86RF232 receiver is split into an analog radio front-end and a digital base
band processor (RX BBP), see Figure 9-1 .
Figure 9-1. Receiver Block Diagram.
LO
Analog Domain
Frame
Digital Domain
Buffer
RFP
LNA
PPF
BPF
Limiter
ADC
RX BBP
SPI
SPI
I/F
RFN
AGC
RSSI
Control, Registers
μC
I/F
The differential RF signal is amplified by a low noise amplifier (LNA), filtered (PPF) and
down converted to an intermediate frequency by a mixer. Channel selectivity is
performed using an integrated band pass filter (BPF). A limiting amplifier (Limiter)
provides sufficient gain to overcome the DC offset of the succeeding analog-to-digital
converter (ADC) and generates a digital RSSI signal. The ADC output signal is sampled
and processed further by the digital base band receiver (RX BBP).
The RX BBP performs additional signal filtering and signal synchronization. The
frequency offset of each frame is calculated by the synchronization unit and is used
during the remaining receive process to correct the offset. The receiver is designed to
handle frequency and symbol rate deviations f SRD up to ±120ppm, caused by combined
receiver and transmitter deviations. For details refer to Section 12.5 parameter f SRD .
Finally the signal is demodulated and the data are stored in the Frame Buffer.
In Basic Operating Mode, refer to Section 7.1 , the reception of a frame is indicated by
an interrupt IRQ_2 (RX_START). Accordingly its end is signalized by an interrupt
IRQ_3 (TRX_END). Based on the quality of the received signal a link quality indicator
(LQI) is calculated and appended to the frame, refer to Section 8.6 . Additional signal
processing is applied to the frame data to provide further status information like ED
value (register 0x07,
PHY_ED_LEVEL)
and FCS correctness (register 0x06,
PHY_RSSI).
Beyond these features the Extended Operating Mode of the AT86RF232 supports
address filtering and pending data indication. For details refer to Section 7.2 .
9.1.2 Frame Receive Procedure
The frame receive procedure including the radio transceiver setup for reception and
reading PSDU data from the Frame Buffer is described in Section 10.1 Frame Receive
Procedure.
9.1.3 Configuration
In Basic Operating Mode the receiver is enabled by writing command RX_ON to
register bits TRX_CMD (register 0x02, TRX_STATE) in states TRX_OFF or PLL_ON.
Similarly in Extended Operating Mode, the receiver is enabled for RX_AACK operation
100
AT86RF232
8321A – MCU Wireless – 10/11
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